module ctrlpath
		(
		clock, resetn,

		zero_a, zero_b,
		
		branch, decabnz, decbbnz,
		ioset, loada, loadb,
		swait,
		ramp, rsram, rlta,

		int_tmr,
		rDIPSW,
		
		load_pc, cnten_pc, sclr_pc,
		load_opc, load_opr,
		load_a, cntdn_a, sclr_a,
		load_b, cntdn_b, sclr_b,
		load_cntref, cnten_tmr, sclr_tmr,
		init_porta, load_porta, init_portb, load_portb,
		sel_portb, PBADDR
		);
input			clock, resetn;
input			zero_a, zero_b;

input			branch, decabnz, decbbnz;
input			ioset, loada, loadb;
input			swait;
input			ramp, rsram, rlta;

input			int_tmr;
input	[3:0]	rDIPSW;

output			load_pc, cnten_pc, sclr_pc;
output			load_opc, load_opr;
output			load_a, cntdn_a, sclr_a;
output			load_b, cntdn_b, sclr_b;
output			load_cntref, cnten_tmr, sclr_tmr;
output			init_porta, load_porta, init_portb, load_portb;
output			sel_portb;
output	[5:0]	PBADDR;

reg				load_pc, cnten_pc, sclr_pc;
reg				load_opc, load_opr;
reg				load_a, cntdn_a, sclr_a;
reg				load_b, cntdn_b, sclr_b;
reg				load_cntref, cnten_tmr, sclr_tmr;
reg				init_porta, load_porta, init_portb, load_portb;
reg				sel_portb;
reg		[5:0]	PBADDR;

wire			run;
assign			run = rDIPSW[3];

parameter [5:0] IDLE  = 0, FETCH = 1, DECODE = 2, WB = 3,
				brEXEC = 4,
				baEXEC = 5, baCHKA = 6, baSETPC = 7,
				bbEXEC = 8, bbCHKB = 9,
				ioEXEC = 11,
				laEXEC = 12,
				lbEXEC = 13,
				waEXEC = 14, waWAIT = 15,
				raEXEC = 16, raINIT = 17, raLATCH = 18, raCOMPARE = 19,
				raFIN1 = 20, raFIN2 = 21, raFIN3 = 22,
				srEXEC = 23, srINIT = 24, srPRECH = 25, srSENSE = 26,
				srLATCH1 = 27, srWAIT1 = 28, srLATCH2 = 29, srWAIT2 = 30,
				srPODODD = 31,
				ltEXEC = 32, ltINIT1 = 33, ltINIT2 = 34, ltWAIT = 35,
				ltLATCH = 36,
				FIN = 37;
reg		[5:0]	STATE;

always @(posedge clock or negedge resetn)
begin: NEXT_CURR
	if (~resetn)	STATE <= IDLE;
	else
		case (STATE)
		IDLE:
			if (~run)
				STATE <= IDLE;
			else
				STATE <= FETCH;
		FETCH:	STATE <= DECODE;
		DECODE:
			if (branch)
				STATE <= brEXEC;
			else if (decabnz)
				STATE <= baEXEC;
			else if (decbbnz)
				STATE <= bbEXEC;
			else if (ioset)
				STATE <= ioEXEC;
			else if (loada)
				STATE <= laEXEC;
			else if (loadb)
				STATE <= lbEXEC;
			else if (swait)
				STATE <= waEXEC;
			else if (ramp)
				STATE <= raEXEC;
			else if (rsram)
				STATE <= srEXEC;
			else if (rlta)
				STATE <= ltEXEC;
			else
				STATE <= IDLE;
		WB:
			if (~run)
				STATE <= IDLE;
			else
				STATE <= FETCH;
		brEXEC:	STATE <= WB;
		baEXEC: STATE <= baCHKA;
		baCHKA:
			if (~zero_a)
				STATE <= baSETPC;
			else
				STATE <= WB;
		baSETPC: STATE <= WB;
		bbEXEC: STATE <= bbCHKB;
		bbCHKB:
			if (~zero_b)
				STATE <= baSETPC;
			else
				STATE <= WB;
		ioEXEC:	STATE <= WB;
		laEXEC: STATE <= WB;
		lbEXEC: STATE <= WB;
		waEXEC: STATE <= waWAIT;
		waWAIT:
			if (~int_tmr)
				STATE <= waWAIT;
			else
				STATE <= WB;
		raEXEC:	STATE <= raINIT;
		raINIT:	STATE <= raLATCH;
		raLATCH: STATE <= raCOMPARE;
		raCOMPARE:
			if (~int_tmr)
				STATE <= raLATCH;
			else
				STATE <= raFIN1;
		raFIN1: STATE <= raFIN2;
		raFIN2: STATE <= raFIN3;
		raFIN3: STATE <= FIN;

		srEXEC: STATE <= srINIT;
		srINIT:	STATE <= srPRECH;
		srPRECH: STATE <= srSENSE;
		srSENSE: STATE <= srLATCH1;
		srLATCH1: STATE <= srWAIT1;
		srWAIT1: STATE <= srLATCH2;
		srLATCH2: STATE <= srWAIT2;
		srWAIT2: STATE <= srPODODD;
		srPODODD:
			if (~int_tmr)
				STATE <= srPRECH;
			else
				STATE <= FIN;
		ltEXEC: STATE <= ltINIT1;
		ltINIT1: STATE <= ltINIT2;
		ltINIT2: STATE <= ltWAIT;
		ltWAIT:	STATE <= ltLATCH;
		ltLATCH:
			if (~int_tmr)
				STATE <= ltWAIT;
			else
				STATE <= FIN;
		FIN:
			if (~run)
				STATE <= IDLE;
			else
				STATE <= FETCH;
		default: STATE <= IDLE;
		endcase
end

always @(STATE)
begin: OUT_LOGIC
	case (STATE)
	IDLE:
		begin
			load_pc      = 0;    cnten_pc      = 0;    sclr_pc   = 1;
			load_opc     = 0;    load_opr      = 0;
			load_a       = 0;    cntdn_a       = 0;    sclr_a    = 1;
			load_b       = 0;    cntdn_b       = 0;    sclr_b    = 1;
			load_cntref  = 0;    cnten_tmr     = 0;    sclr_tmr  = 1;
			init_porta   = 1;    init_portb    = 1;
			load_porta   = 0;    load_portb    = 0;    sel_portb = 0;
			PBADDR = 6'b00_0000;
		end
	FETCH:
		begin
			load_pc      = 0;    cnten_pc      = 1;    sclr_pc   = 0;
			load_opc     = 1;    load_opr      = 1;
			load_a       = 0;    cntdn_a       = 0;    sclr_a    = 0;
			load_b       = 0;    cntdn_b       = 0;    sclr_b    = 0;
			load_cntref  = 0;    cnten_tmr     = 0;    sclr_tmr  = 0;
			init_porta   = 0;    init_portb    = 0;
			load_porta   = 0;    load_portb    = 0;    sel_portb = 0;
			PBADDR = 6'b00_0000;
		end
	DECODE:
		begin
			load_pc      = 0;    cnten_pc      = 0;    sclr_pc   = 0;
			load_opc     = 0;    load_opr      = 0;
			load_a       = 0;    cntdn_a       = 0;    sclr_a    = 0;
			load_b       = 0;    cntdn_b       = 0;    sclr_b    = 0;
			load_cntref  = 0;    cnten_tmr     = 0;    sclr_tmr  = 0;
			init_porta   = 0;    init_portb    = 0;
			load_porta   = 0;    load_portb    = 0;    sel_portb = 0;
			PBADDR = 6'b00_0000;
		end
	WB:
		begin
			load_pc      = 0;    cnten_pc      = 0;    sclr_pc   = 0;
			load_opc     = 0;    load_opr      = 0;
			load_a       = 0;    cntdn_a       = 0;    sclr_a    = 0;
			load_b       = 0;    cntdn_b       = 0;    sclr_b    = 0;
			load_cntref  = 0;    cnten_tmr     = 0;    sclr_tmr  = 0;
			init_porta   = 0;    init_portb    = 0;
			load_porta   = 0;    load_portb    = 0;    sel_portb = 0;
			PBADDR = 6'b00_0000;
		end
	brEXEC:
		begin
			load_pc      = 1;    cnten_pc      = 0;    sclr_pc   = 0;
			load_opc     = 0;    load_opr      = 0;
			load_a       = 0;    cntdn_a       = 0;    sclr_a    = 0;
			load_b       = 0;    cntdn_b       = 0;    sclr_b    = 0;
			load_cntref  = 0;    cnten_tmr     = 0;    sclr_tmr  = 0;
			init_porta   = 0;    init_portb    = 0;
			load_porta   = 0;    load_portb    = 0;    sel_portb = 0;
			PBADDR = 6'b00_0000;
		end
	baEXEC:
		begin
			load_pc      = 0;    cnten_pc      = 0;    sclr_pc   = 0;
			load_opc     = 0;    load_opr      = 0;
			load_a       = 0;    cntdn_a       = 1;    sclr_a    = 0;
			load_b       = 0;    cntdn_b       = 0;    sclr_b    = 0;
			load_cntref  = 0;    cnten_tmr     = 0;    sclr_tmr  = 0;
			init_porta   = 0;    init_portb    = 0;
			load_porta   = 0;    load_portb    = 0;    sel_portb = 0;
			PBADDR = 6'b00_0000;
		end
	baCHKA:
		begin
			load_pc      = 0;    cnten_pc      = 0;    sclr_pc   = 0;
			load_opc     = 0;    load_opr      = 0;
			load_a       = 0;    cntdn_a       = 0;    sclr_a    = 0;
			load_b       = 0;    cntdn_b       = 0;    sclr_b    = 0;
			load_cntref  = 0;    cnten_tmr     = 0;    sclr_tmr  = 0;
			init_porta   = 0;    init_portb    = 0;
			load_porta   = 0;    load_portb    = 0;    sel_portb = 0;
			PBADDR = 6'b00_0000;
		end
	baSETPC:
		begin
			load_pc      = 1;    cnten_pc      = 0;    sclr_pc   = 0;
			load_opc     = 0;    load_opr      = 0;
			load_a       = 0;    cntdn_a       = 0;    sclr_a    = 0;
			load_b       = 0;    cntdn_b       = 0;    sclr_b    = 0;
			load_cntref  = 0;    cnten_tmr     = 0;    sclr_tmr  = 0;
			init_porta   = 0;    init_portb    = 0;
			load_porta   = 0;    load_portb    = 0;    sel_portb = 0;
			PBADDR = 6'b00_0000;
		end
	bbEXEC:
		begin
			load_pc      = 0;    cnten_pc      = 0;    sclr_pc   = 0;
			load_opc     = 0;    load_opr      = 0;
			load_a       = 0;    cntdn_a       = 0;    sclr_a    = 0;
			load_b       = 0;    cntdn_b       = 1;    sclr_b    = 0;
			load_cntref  = 0;    cnten_tmr     = 0;    sclr_tmr  = 0;
			init_porta   = 0;    init_portb    = 0;
			load_porta   = 0;    load_portb    = 0;    sel_portb = 0;
			PBADDR = 6'b00_0000;
		end
	bbCHKB:
		begin
			load_pc      = 0;    cnten_pc      = 0;    sclr_pc   = 0;
			load_opc     = 0;    load_opr      = 0;
			load_a       = 0;    cntdn_a       = 0;    sclr_a    = 0;
			load_b       = 0;    cntdn_b       = 0;    sclr_b    = 0;
			load_cntref  = 0;    cnten_tmr     = 0;    sclr_tmr  = 0;
			init_porta   = 0;    init_portb    = 0;
			load_porta   = 0;    load_portb    = 0;    sel_portb = 0;
			PBADDR = 6'b00_0000;
		end
	ioEXEC:
		begin
			load_pc      = 0;    cnten_pc      = 0;    sclr_pc   = 0;
			load_opc     = 0;    load_opr      = 0;
			load_a       = 0;    cntdn_a       = 0;    sclr_a    = 0;
			load_b       = 0;    cntdn_b       = 0;    sclr_b    = 0;
			load_cntref  = 0;    cnten_tmr     = 0;    sclr_tmr  = 0;
			init_porta   = 0;    init_portb    = 0;
			load_porta   = 1;    load_portb    = 1;    sel_portb = 0;
			PBADDR = 6'b00_0000;
		end
	laEXEC:
		begin
			load_pc      = 0;    cnten_pc      = 0;    sclr_pc   = 0;
			load_opc     = 0;    load_opr      = 0;
			load_a       = 1;    cntdn_a       = 0;    sclr_a    = 0;
			load_b       = 0;    cntdn_b       = 0;    sclr_b    = 0;
			load_cntref  = 0;    cnten_tmr     = 0;    sclr_tmr  = 0;
			init_porta   = 0;    init_portb    = 0;
			load_porta   = 0;    load_portb    = 0;    sel_portb = 0;
			PBADDR = 6'b00_0000;
		end
	lbEXEC:
		begin
			load_pc      = 0;    cnten_pc      = 0;    sclr_pc   = 0;
			load_opc     = 0;    load_opr      = 0;
			load_a       = 0;    cntdn_a       = 0;    sclr_a    = 0;
			load_b       = 1;    cntdn_b       = 0;    sclr_b    = 0;
			load_cntref  = 0;    cnten_tmr     = 0;    sclr_tmr  = 0;
			init_porta   = 0;    init_portb    = 0;
			load_porta   = 0;    load_portb    = 0;    sel_portb = 0;
			PBADDR = 6'b00_0000;
		end
	waEXEC:
		begin
			load_pc      = 0;    cnten_pc      = 0;    sclr_pc   = 0;
			load_opc     = 0;    load_opr      = 0;
			load_a       = 0;    cntdn_a       = 0;    sclr_a    = 0;
			load_b       = 0;    cntdn_b       = 0;    sclr_b    = 0;
			load_cntref  = 1;    cnten_tmr     = 0;    sclr_tmr  = 1;
			init_porta   = 0;    init_portb    = 0;
			load_porta   = 0;    load_portb    = 0;    sel_portb = 0;
			PBADDR = 6'b00_0000;
		end
	waWAIT:
		begin
			load_pc      = 0;    cnten_pc      = 0;    sclr_pc   = 0;
			load_opc     = 0;    load_opr      = 0;
			load_a       = 0;    cntdn_a       = 0;    sclr_a    = 0;
			load_b       = 0;    cntdn_b       = 0;    sclr_b    = 0;
			load_cntref  = 0;    cnten_tmr     = 1;    sclr_tmr  = 0;
			init_porta   = 0;    init_portb    = 0;
			load_porta   = 0;    load_portb    = 0;    sel_portb = 0;
			PBADDR = 6'b00_0000;
		end
	raEXEC:
		begin
			load_pc      = 0;    cnten_pc      = 0;    sclr_pc   = 0;
			load_opc     = 0;    load_opr      = 0;
			load_a       = 0;    cntdn_a       = 0;    sclr_a    = 0;
			load_b       = 0;    cntdn_b       = 0;    sclr_b    = 0;
			load_cntref  = 1;    cnten_tmr     = 0;    sclr_tmr  = 1;
			init_porta   = 0;    init_portb    = 0;
			load_porta   = 0;    load_portb    = 0;    sel_portb = 1;
			PBADDR = 6'b00_0000;
		end
	raINIT:
		begin
			load_pc      = 0;    cnten_pc      = 0;    sclr_pc   = 0;
			load_opc     = 0;    load_opr      = 0;
			load_a       = 0;    cntdn_a       = 0;    sclr_a    = 0;
			load_b       = 0;    cntdn_b       = 0;    sclr_b    = 0;
			load_cntref  = 0;    cnten_tmr     = 0;    sclr_tmr  = 0;
			init_porta   = 0;    init_portb    = 0;
			load_porta   = 0;    load_portb    = 1;    sel_portb = 1;
			PBADDR = 6'b00_0001;
		end
	raLATCH:
		begin
			load_pc      = 0;    cnten_pc      = 0;    sclr_pc   = 0;
			load_opc     = 0;    load_opr      = 0;
			load_a       = 0;    cntdn_a       = 0;    sclr_a    = 0;
			load_b       = 0;    cntdn_b       = 0;    sclr_b    = 0;
			load_cntref  = 0;    cnten_tmr     = 1;    sclr_tmr  = 0;
			init_porta   = 0;    init_portb    = 0;
			load_porta   = 0;    load_portb    = 1;    sel_portb = 1;
			PBADDR = 6'b00_0010;
		end
	raCOMPARE:
		begin
			load_pc      = 0;    cnten_pc      = 0;    sclr_pc   = 0;
			load_opc     = 0;    load_opr      = 0;
			load_a       = 0;    cntdn_a       = 0;    sclr_a    = 0;
			load_b       = 0;    cntdn_b       = 0;    sclr_b    = 0;
			load_cntref  = 0;    cnten_tmr     = 0;    sclr_tmr  = 0;
			init_porta   = 0;    init_portb    = 0;
			load_porta   = 0;    load_portb    = 1;    sel_portb = 1;
			PBADDR = 6'b00_0011;
		end
	raFIN1:
		begin
			load_pc      = 0;    cnten_pc      = 0;    sclr_pc   = 0;
			load_opc     = 0;    load_opr      = 0;
			load_a       = 0;    cntdn_a       = 0;    sclr_a    = 0;
			load_b       = 0;    cntdn_b       = 0;    sclr_b    = 0;
			load_cntref  = 0;    cnten_tmr     = 0;    sclr_tmr  = 0;
			init_porta   = 0;    init_portb    = 0;
			load_porta   = 0;    load_portb    = 1;    sel_portb = 1;
			PBADDR = 6'b00_0100;
		end
	raFIN2:
		begin
			load_pc      = 0;    cnten_pc      = 0;    sclr_pc   = 0;
			load_opc     = 0;    load_opr      = 0;
			load_a       = 0;    cntdn_a       = 0;    sclr_a    = 0;
			load_b       = 0;    cntdn_b       = 0;    sclr_b    = 0;
			load_cntref  = 0;    cnten_tmr     = 0;    sclr_tmr  = 0;
			init_porta   = 0;    init_portb    = 0;
			load_porta   = 0;    load_portb    = 1;    sel_portb = 1;
			PBADDR = 6'b00_0101;
		end
	raFIN3:
		begin
			load_pc      = 0;    cnten_pc      = 0;    sclr_pc   = 0;
			load_opc     = 0;    load_opr      = 0;
			load_a       = 0;    cntdn_a       = 0;    sclr_a    = 0;
			load_b       = 0;    cntdn_b       = 0;    sclr_b    = 0;
			load_cntref  = 0;    cnten_tmr     = 0;    sclr_tmr  = 0;
			init_porta   = 0;    init_portb    = 0;
			load_porta   = 0;    load_portb    = 1;    sel_portb = 1;
			PBADDR = 6'b00_0110;
		end
	srEXEC:
		begin
			load_pc      = 0;    cnten_pc      = 0;    sclr_pc   = 0;
			load_opc     = 0;    load_opr      = 0;
			load_a       = 0;    cntdn_a       = 0;    sclr_a    = 0;
			load_b       = 0;    cntdn_b       = 0;    sclr_b    = 0;
			load_cntref  = 1;    cnten_tmr     = 0;    sclr_tmr  = 1;
			init_porta   = 0;    init_portb    = 0;
			load_porta   = 0;    load_portb    = 0;    sel_portb = 1;
			PBADDR = 6'b00_0000;
		end
	srINIT:
		begin
			load_pc      = 0;    cnten_pc      = 0;    sclr_pc   = 0;
			load_opc     = 0;    load_opr      = 0;
			load_a       = 0;    cntdn_a       = 0;    sclr_a    = 0;
			load_b       = 0;    cntdn_b       = 0;    sclr_b    = 0;
			load_cntref  = 0;    cnten_tmr     = 0;    sclr_tmr  = 0;
			init_porta   = 0;    init_portb    = 0;
			load_porta   = 0;    load_portb    = 1;    sel_portb = 1;
			PBADDR = 6'b01_0001;
		end
	srPRECH:
		begin
			load_pc      = 0;    cnten_pc      = 0;    sclr_pc   = 0;
			load_opc     = 0;    load_opr      = 0;
			load_a       = 0;    cntdn_a       = 0;    sclr_a    = 0;
			load_b       = 0;    cntdn_b       = 0;    sclr_b    = 0;
			load_cntref  = 0;    cnten_tmr     = 1;    sclr_tmr  = 0;
			init_porta   = 0;    init_portb    = 0;
			load_porta   = 0;    load_portb    = 1;    sel_portb = 1;
			PBADDR = 6'b01_0010;
		end
	srSENSE:
		begin
			load_pc      = 0;    cnten_pc      = 0;    sclr_pc   = 0;
			load_opc     = 0;    load_opr      = 0;
			load_a       = 0;    cntdn_a       = 0;    sclr_a    = 0;
			load_b       = 0;    cntdn_b       = 0;    sclr_b    = 0;
			load_cntref  = 0;    cnten_tmr     = 0;    sclr_tmr  = 0;
			init_porta   = 0;    init_portb    = 0;
			load_porta   = 0;    load_portb    = 1;    sel_portb = 1;
			PBADDR = 6'b01_0011;
		end
	srLATCH1:
		begin
			load_pc      = 0;    cnten_pc      = 0;    sclr_pc   = 0;
			load_opc     = 0;    load_opr      = 0;
			load_a       = 0;    cntdn_a       = 0;    sclr_a    = 0;
			load_b       = 0;    cntdn_b       = 0;    sclr_b    = 0;
			load_cntref  = 0;    cnten_tmr     = 0;    sclr_tmr  = 0;
			init_porta   = 0;    init_portb    = 0;
			load_porta   = 0;    load_portb    = 1;    sel_portb = 1;
			PBADDR = 6'b01_0100;
		end
	srWAIT1:
		begin
			load_pc      = 0;    cnten_pc      = 0;    sclr_pc   = 0;
			load_opc     = 0;    load_opr      = 0;
			load_a       = 0;    cntdn_a       = 0;    sclr_a    = 0;
			load_b       = 0;    cntdn_b       = 0;    sclr_b    = 0;
			load_cntref  = 0;    cnten_tmr     = 0;    sclr_tmr  = 0;
			init_porta   = 0;    init_portb    = 0;
			load_porta   = 0;    load_portb    = 1;    sel_portb = 1;
			PBADDR = 6'b01_0101;
		end
	srLATCH2:
		begin
			load_pc      = 0;    cnten_pc      = 0;    sclr_pc   = 0;
			load_opc     = 0;    load_opr      = 0;
			load_a       = 0;    cntdn_a       = 0;    sclr_a    = 0;
			load_b       = 0;    cntdn_b       = 0;    sclr_b    = 0;
			load_cntref  = 0;    cnten_tmr     = 0;    sclr_tmr  = 0;
			init_porta   = 0;    init_portb    = 0;
			load_porta   = 0;    load_portb    = 1;    sel_portb = 1;
			PBADDR = 6'b01_0110;
		end
	srWAIT2:
		begin
			load_pc      = 0;    cnten_pc      = 0;    sclr_pc   = 0;
			load_opc     = 0;    load_opr      = 0;
			load_a       = 0;    cntdn_a       = 0;    sclr_a    = 0;
			load_b       = 0;    cntdn_b       = 0;    sclr_b    = 0;
			load_cntref  = 0;    cnten_tmr     = 0;    sclr_tmr  = 0;
			init_porta   = 0;    init_portb    = 0;
			load_porta   = 0;    load_portb    = 1;    sel_portb = 1;
			PBADDR = 6'b01_0111;
		end
	srPODODD:
		begin
			load_pc      = 0;    cnten_pc      = 0;    sclr_pc   = 0;
			load_opc     = 0;    load_opr      = 0;
			load_a       = 0;    cntdn_a       = 0;    sclr_a    = 0;
			load_b       = 0;    cntdn_b       = 0;    sclr_b    = 0;
			load_cntref  = 0;    cnten_tmr     = 0;    sclr_tmr  = 0;
			init_porta   = 0;    init_portb    = 0;
			load_porta   = 0;    load_portb    = 1;    sel_portb = 1;
			PBADDR = 6'b01_1000;
		end
	ltEXEC:
		begin
			load_pc      = 0;    cnten_pc      = 0;    sclr_pc   = 0;
			load_opc     = 0;    load_opr      = 0;
			load_a       = 0;    cntdn_a       = 0;    sclr_a    = 0;
			load_b       = 0;    cntdn_b       = 0;    sclr_b    = 0;
			load_cntref  = 1;    cnten_tmr     = 0;    sclr_tmr  = 1;
			init_porta   = 0;    init_portb    = 0;
			load_porta   = 0;    load_portb    = 0;    sel_portb = 1;
			PBADDR = 6'b00_0000;
		end
	ltINIT1:
		begin
			load_pc      = 0;    cnten_pc      = 0;    sclr_pc   = 0;
			load_opc     = 0;    load_opr      = 0;
			load_a       = 0;    cntdn_a       = 0;    sclr_a    = 0;
			load_b       = 0;    cntdn_b       = 0;    sclr_b    = 0;
			load_cntref  = 0;    cnten_tmr     = 0;    sclr_tmr  = 0;
			init_porta   = 0;    init_portb    = 0;
			load_porta   = 0;    load_portb    = 1;    sel_portb = 1;
			PBADDR = 6'b10_0001;
		end
	ltINIT2:
		begin
			load_pc      = 0;    cnten_pc      = 0;    sclr_pc   = 0;
			load_opc     = 0;    load_opr      = 0;
			load_a       = 0;    cntdn_a       = 0;    sclr_a    = 0;
			load_b       = 0;    cntdn_b       = 0;    sclr_b    = 0;
			load_cntref  = 0;    cnten_tmr     = 0;    sclr_tmr  = 0;
			init_porta   = 0;    init_portb    = 0;
			load_porta   = 0;    load_portb    = 1;    sel_portb = 1;
			PBADDR = 6'b10_0010;
		end
	ltWAIT:
		begin
			load_pc      = 0;    cnten_pc      = 0;    sclr_pc   = 0;
			load_opc     = 0;    load_opr      = 0;
			load_a       = 0;    cntdn_a       = 0;    sclr_a    = 0;
			load_b       = 0;    cntdn_b       = 0;    sclr_b    = 0;
			load_cntref  = 0;    cnten_tmr     = 1;    sclr_tmr  = 0;
			init_porta   = 0;    init_portb    = 0;
			load_porta   = 0;    load_portb    = 1;    sel_portb = 1;
			PBADDR = 6'b10_0011;
		end
	ltLATCH:
		begin
			load_pc      = 0;    cnten_pc      = 0;    sclr_pc   = 0;
			load_opc     = 0;    load_opr      = 0;
			load_a       = 0;    cntdn_a       = 0;    sclr_a    = 0;
			load_b       = 0;    cntdn_b       = 0;    sclr_b    = 0;
			load_cntref  = 0;    cnten_tmr     = 0;    sclr_tmr  = 0;
			init_porta   = 0;    init_portb    = 0;
			load_porta   = 0;    load_portb    = 1;    sel_portb = 1;
			PBADDR = 6'b10_0100;
		end
	FIN:
		begin
			load_pc      = 0;    cnten_pc      = 0;    sclr_pc   = 0;
			load_opc     = 0;    load_opr      = 0;
			load_a       = 0;    cntdn_a       = 0;    sclr_a    = 0;
			load_b       = 0;    cntdn_b       = 0;    sclr_b    = 0;
			load_cntref  = 0;    cnten_tmr     = 0;    sclr_tmr  = 0;
			init_porta   = 0;    init_portb    = 0;
			load_porta   = 0;    load_portb    = 1;    sel_portb = 1;
			PBADDR = 6'b00_0000;
		end
	default:
		begin
			load_pc      = 0;    cnten_pc      = 0;    sclr_pc   = 1;
			load_opc     = 0;    load_opr      = 0;
			load_a       = 0;    cntdn_a       = 0;    sclr_a    = 1;
			load_b       = 0;    cntdn_b       = 0;    sclr_b    = 1;
			load_cntref  = 0;    cnten_tmr     = 0;    sclr_tmr  = 1;
			init_porta   = 1;    init_portb    = 1;
			load_porta   = 0;    load_portb    = 0;    sel_portb = 0;
			PBADDR = 6'b00_0000;
		end
	endcase
end
endmodule